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description the M37733S4BFP is a microcomputer using the 7700 family core. this microcomputer has a cpu and a bus interface unit. the cpu is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. this microcomputer also includes a 32 khz oscillation circuit, in addition to the ram, multiple-function timers, serial i/o, a-d converter, and so on. features l number of basic instructions .................................................. 103 l memory size ram ................................................ 2048 bytes l instruction execution time the fastest instruction at 25 mhz frequency ...................... 160 ns l single power supply .................................................... 5 v 10 % l low power dissipation (at 25 mhz frequency)....... 47.5 mw (typ.) l interrupts ............................................................ 19 types, 7 levels l multiple-function 16-bit timer ................................................. 5 + 3 l serial i/o (uart or clock synchronous)..................................... 3 l 10-bit a-d converter .............................................. 8-channel inputs l 12-bit watchdog timer l programmable input/output (ports p4, p5, p6, p7, p8) ........................................................ 37 l clock generating circuit ........................................ 2 circuits built-in application control devices for general commercial equipment such as office automation, office equipment, personal information equipment, and so on. control devices for general industrial equipment such as communication equipment, and so on. pin configuration (top view) mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product outline 80p6n-a 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 p2 4 /a 20 /d 4 p2 5 /a 21 /d 5 p2 6 /a 22 /d 6 p2 7 /a 23 /d 7 p3 0 / r / w p3 1 / bhe p3 2 /ale p3 3 / hlda v ss e x out x in reset cnv ss byte hold 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p8 4 / cts 1 / rts 1 p8 5 /clk 1 p8 6 /r x d 1 p8 7 /t x d 1 p0 0 /a 0 p0 1 /a 1 p0 2 /a 2 p0 3 /a 3 p0 4 /a 4 p0 5 /a 5 p0 6 /a 6 p0 7 /a 7 p1 0 /a 8 /d 8 p1 1 /a 9 /d 9 p1 2 /a 10 /d 10 p1 3 /a 11 /d 11 p1 4 /a 12 /d 12 p1 5 /a 13 /d 13 p1 6 /a 14 /d 14 p1 7 /a 15 /d 15 p2 0 /a 16 /d 0 p2 1 /a 17 /d 1 p2 2 /a 18 /d 2 p2 3 /a 19 /d 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p8 3 /t x d 0 p8 2 /r x d 0 /clks 0 p8 1 /clk 0 p8 0 / cts 0 / rts 0 /clks 1 v cc av cc v ref av ss v ss p7 7 /an 7 /x cin p7 6 /an 6 /x cout p7 5 /an 5 / ad trg /t x d 2 p7 4 /an 4 /r x d 2 p7 3 /an 3 /clk 2 p7 2 /an 2 / cts 2 p7 1 /an 1 p7 0 /an 0 p6 7 /tb2 in / sub p6 6 /tb1 in p6 5 /tb0 in p6 4 / int 2 p6 3 / int 1 p6 2 / int 0 p6 1 /ta4 in p6 0 /ta4 out p5 7 /ta3 in / ki 3 /rtp1 3 p5 6 /ta3 out / ki 2 /rtp1 2 p5 5 /ta2 in / ki 1 /rtp1 1 p5 4 /ta2 out / ki 0 /rtp1 0 p5 3 /ta1 in /rtp0 3 p5 2 /ta1 out /rtp0 2 p5 1 /ta0 in /rtp0 1 p5 0 /ta0 out /rtp0 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 / 1 rdy M37733S4BFP
2 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product M37733S4BFP block diagram x in x out e reset reset input v ref p8(8) p7(8) p5(8) p6(8) p4(5) address higher middler/data (16) cnvss byte address lower (8) uart1(9) uart0(9) av ss (0v) av cc (0v) v ss v cc x cin x cout x cin x cout clock input clock output enable output reference voltage input external data bus width selection input clock generating circuit instruction register(8) arithmetic logic unit(16) accumulator a(16) accumulator b(16) index register x(16) index register y(16) stack pointer s(16) direct page register dpr(16) processor status register ps(11) input butter register ib(16) data bank register dt(8) program bank register pg(8) program counter pc(16) incrementer/decrementer(24) data address register da(24) program address register pa(24) incrementer(24) instruction queue buffer q 2 (8) instruction queue buffer q 1 (8) instruction queue buffer q 0 (8) data buffer db l (8) data buffer db h (8) ram 2048 bytes timer ta3(16) timer ta4(16) timer ta2(16) timer ta1(16) timer ta0(16) watchdog timer timer tb2(16) timer tb1(16) timer tb0(16) address bus data bus(odd) data bus(even) input/output port p8 input/output port p7 input/output port p6 input/output port p5 input/output port p4 address bus/data bus address bus uart2(9) r/ w bhe ale hlda hold rdy 1 a-d converter(10)
3 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product parameter functions number of basic instructions 103 instruction execution time 160 ns (the fastest instruction at external clock 25 mhz frequency) memory size ram 2048 bytes p5 C p8 8-bit 5 4 p4 5-bit 5 1 ta0, ta1, ta2, ta3, ta4 16-bit 5 5 tb0, tb1, tb2 16-bit 5 3 serial i/o (uart or clock synchronous serial i/o) 5 3 a-d converter 10-bit 5 1 (8 channels) watchdog timer 12-bit 5 1 3 external types, 16 internal types each interrupt can be set to the priority level (0 C 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) supply voltage 5 v 10 % power dissipation 47.5 mw (at external clock 25 mhz frequency) input/output voltage 5 v output current 5 ma memory expansion maximum 16 mbytes operating temperature range C20 to 85 c device structure cmos high-performance silicon gate process package 80-pin plastic molded qfp (80p6n-a) functions of M37733S4BFP input/output ports multi-function timers interrupts clock generating circuit input/output characteristic
4 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product pin description x in clock input input x out clock output output pin name input/output functions vcc, power source apply 5 v 10 % to vcc and 0 v to vss. vss cnvss cnvss input input connect to vcc. _____ reset reset input input when l level is applied to this pin, the microcomputer enters the reset state. these are pins of main-clock generating circuit. connect a ceramic resonator or a quartz-crystal oscillator between x in and x out . when an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. _ e enable output output _ when output level of e signal is l, data/instruction read or data write is performed. byte bus width input this pin determines whether the external data bus has an 8-bit width or a 16-bit width. selection input the data bus has a 16-bit width when l signal is input and an 8-bit width when h signal is input. avcc, analog power power source input pin for the a-d converter. externally connect avcc to vcc and avss to vss. avss source input v ref reference input this is reference voltage input pin for the a-d converter. voltage input p0 0 /a 0 C address (low- output address (a 0 C a 7 ) is output. p0 7 /a 7 order) output p1 0 /a 8 /d 8 C address (middle i/o when the byte pin is set to l and external data bus has a 16-bit width, high-order data p1 7 /a 15 /d 15 -order) (d 8 C d 15 ) is input/output or an address (a 8 C a 15 ) is output. when the byte pin is h and an output/data external data bus has an 8-bit width, only address (a 8 C a 15 ) is output. (high-order) i/o p2 0 /a 16 /d 0 C address (high- i/o low-order data (d 0 C d 7 ) is input/output or an address (a 16 C a 23 ) is output. p2 7 /a 23 /d 7 order) output/data (low-order) i/o _ p3 0 /r/ w read/write output h indicates the read status and l indicates the write status. output ___ p3 1 / bhe byte high output l is output when an odd-numbered address is accessed. enable output p3 2 /ale address latch output this is used to retrieve only the address from address and data multiplex signal. enable output ____ p3 3 / hlda hold acknow- output this outputs l level when the microcomputer enters hold state after a hold request is accepted. ledge output ____ hold hold request input ____ this is an input pin for hold request signal. the microcomputer enters into hold state while this input signal is l. ___ rdy ready input input ___ this is an input pin for rdy signal. the microcomputer enters into ready state while this signal is l. p4 2 / 1 clock output output this pin outputs the clock 1 . p4 3 C p4 7 i/o port p4 i/o these pins become a 5-bit i/o port. an i/o direction register is available so that each pin can be programmed for input or output. these ports are in the input mode when reset. p5 0 C p5 7 i/o port p5 i/o in addition to having the same functions as port p4, these pins also function as i/o pins for timers __ __ a0 to a3 and input pins for key input interrupt input ( ki 0 C ki 3 ). p6 0 C p6 7 i/o port p6 i/o in addition to having the same functions as port p4, these pins also function as i/o pins for timer ___ ___ a4, input pins for external interrupt input ( int 0 C int 2 ) and input pins for timers b0 to b2. p6 7 also functions as sub-clock sub output pin. p7 0 C p7 7 i/o port p7 i/o in addition to having the same functions as port p4, these pins function as input pins for a-d converter. p7 2 to p7 5 also function as i/o pins for uart2. additionally, p7 6 and p7 7 have the function as the output pin (x cout ) and the input pin (x cin ) of the sub-clock (32 khz) oscillation circuit, respectively. when p7 6 and p7 7 are used as the x cout and x cin pins, connect a resonator or an oscillator between the both. p8 0 C p8 7 i/o port p8 i/o in addition to having the same functions as port p4, these pins also function as i/o pins for uart 0 and uart 1.
5 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product fig. 1 memory map basic function blocks the M37733S4BFP has the same functions as the m37733mhbxxxfp except for the following : (1) the memory map is different. (2) the processor mode is different. (3) the reset circuit is different. (4) pulse output port mode of timer a is available. (5) the function of rom area modification is not available. memory the memory map is shown in figure 1. the address space has a capacity of 16 mbytes and is allocated to addresses from 0 16 to ffffff 16 . the address space is divided by 64-kbyte unit called bank. the banks are numbered from 0 16 to ff 16 . built-in ram and control registers for internal peripheral devices are assigned to bank 0 16 . addresses ffd6 16 to ffff 16 are the reset and interrupt vector addresses and contain the interrupt vectors. use rom for memory of this address. the 2048-byte area allocated to addresses from 80 16 to 87f 16 is the built-in ram. in addition to storing data, the ram is used as stack during a subroutine call or interrupts. peripheral devices such as i/o ports, a-d converter, serial i/o, timer, and interrupt control registers are allocated to addresses from 0 16 to 7f 16 . a 256-byte direct page area can be allocated anywhere in bank 0 16 by using the direct page register (dpr). in the direct page addressing mode, the memory in the direct page area can be accessed with two words. hence program steps can be reduced. a-d/uart2 trans./rece. timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 /key input int 0 watchdog timer dbc brk instruction zero divide reset internal peripheral devices control registers refer to fig. 2 for detail information interrupt vector table 000000 16 00ffff 16 010000 16 01ffff 16 bank 0 16 bank 1 16 fe0000 16 feffff 16 ff0000 16 ffffff 16 bank ff 16 bank fe 16 00ffff 16 00ffd6 16 00087f 16 000000 16 00007f 16 000080 16 internal ram 2048 bytes 00fffe 16 00ffd6 16 00007f 16 000000 16 uart1 transmission uart1 receive uart0 transmission uart0 receive ??????????????????? int 1 : internal : external
6 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product fig. 2 location of internal peripheral devices and interrupt control registers uart 0 transmission interrupt control register uart 1 transmission interrupt control register int 2 /key input interrupt control register port p1 direction register uart 0 transmit/receive mode register uart 0 baud rate register (brg0) uart 0 transmit/receive control register 0 uart 0 transmit/receive control register 1 uart 0 transmission buffer register uart 1 transmit/receive control register 0 uart 1 transmit/receive mode register uart 1 baud rate register (brg1) uart 1 transmit/receive control register 1 uart 0 receive buffer register uart 1 transmission buffer register uart 1 receive buffer register port p0 register a-d register 0 a-d register 2 port p1 register port p0 direction register port p2 register port p3 register port p4 register port p5 register port p6 register port p7 register port p8 register a-d control register 0 a-d control register 1 a-d register 1 a-d register 3 a-d register 4 a-d register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001a 00001b 00001c 00001d 00001e 00001f 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002a 00002b 00002c 00002d 00002e 00002f 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003a 00003b 00003c 00003d 00003e 00003f 00000b 00000c 00000d 00000e 00000f 00000a 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005a 00005b 00005c 00005d 00005e 00005f 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006a 00006b 00006c 00006d 00006e 00006f 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007a 00007b 00007c 00007d 00007e 00007f 00004b 00004c 00004d 00004e 00004f 00004a 000044 address (hexadecimal notation) address (hexadecimal notation) timer a1 register timer a4 register timer a2 register timer a3 register timer b0 register timer b1 register timer b2 register count start flag one-shot start flag up-down flag timer a0 register timer a0 mode register timer a1 mode register timer a2 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 watchdog timer register watchdog timer frequency selection flag a-d/uart2 trans./rece. interrupt control register uart 0 receive interrupt control register uart 1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register processor mode register 1 oscillation circuit control register 1 serial transmit control register port function control register oscillation circuit control register 0 timer a3 mode register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register pulse output data register 1 pulse output data register 0 a-d register 6 a-d register 7 waveform output mode register uart2 transmit/receive mode register uart2 baud rate register (brg2) uart2 transmission buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register reserved area (note) note . do not write to this address.
7 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product pulse output port mode the pulse motor drive waveform can be output by using plural internal timer a. figure 3 shows a block diagram for pulse output port mode. in the pulse output port mode, two pairs of four-bit pulse output ports are used. whether using pulse output port or not can be selected by waveform output selection bit (bit 0, bit 1) of waveform output mode register (62 16 address) shown in figure 4. when bit 0 of waveform output selection bit is set to 1, rtp1 0 , rtp1 1 , rtp1 2 , and rtp1 3 are used as pulse output ports, and when bit 1 of waveform output selection bit is set to 1, rtp0 0 , rtp0 1 , rtp0 2 , and rtp0 3 are used as pulse output ports. when bits 1 and 0 of waveform output selection bit are set to 1, rtp1 0 , rtp1 1 , rtp1 2 , and rtp1 3 , and rtp0 0 , rtp0 1 , rtp0 2, and rtp0 3 are used as pulse output ports. the ports not used as pulse output ports can be used as normal parallel ports, timer input/output or key input interruput input. in the pulse output port mode, set timers a0 and a2 to timer mode as timers a0 and a2 are used. figure 5 shows the bit configuration of timer a0, a2 mode registers in pulse output port mode. data can be set in each bit of the pulse output data register corresponding to four ports selected as pulse output ports. figure 6 shows the bit configuration of the pulse output data register. the contents of the pulse output data register 1 (low-order four bits of 1c 16 address) corresponding to rtp1 0 , rtp1 1 , rtp1 2 , and rtp1 3 is output to the ports each time the counter of timer a2 becomes 0000 16 . the contents of the pulse output data register 0 (low-order four bits of 1d 16 address) corresponding to rtp0 0 , rtp0 1 , rtp0 2 , and rtp0 3 is output to the ports each time the counter of timer a0 becomes 0000 16 . figure 7 shows example of waveforms in pulse output port mode. when 0 is written to a specified bit of the pulse output data register, l level is output to the corresponding pulse output port when the counter of corresponding timer becomes 0000 16 , and when 1 is written, h level is output to the pulse output port. pulse width modulation can be applied to each pulse output port. since pulse width modulation involves the use of timers a1 and a3, activate these timers in pulse width modulation mode. fig. 3 block diagram for pulse output port mode timer a2 pulse width modulation output by timer a3 pulse width modulation output by timer a1 d 3 d 2 d 1 d 0 d d d d q q q q t d 11 d 10 d 9 d 8 d d d d q q q q t timer a0 pulse output data register 0 (1d 16 address) pulse output data register 1 (1c 16 address) pulse width modulation selection bit (bit 4, 5 of 62 16 address) rtp1 3 (p5 7 ) rtp1 2 (p5 6 ) rtp1 1 ( p5 5 ) rtp1 0 (p5 4 ) rtp0 3 (p5 3 ) rtp0 2 (p5 2 ) rtp0 1 (p5 1 ) rtp0 0 (p5 0 ) polarity selection bit (bit 3 of 62 16 address) 45 data bus (odd) data bus (even)
8 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product rtp1 0 , rtp1 1 , rtp1 2 , and rtp1 3 are applied pulse width modulation by timer a3 by setting the pulse width modulation selection bit by timer a3 (bit 5) of the waveform output mode register to 1. rtp0 0 , rtp0 1 , rtp0 2 , and rtp0 3 are applied pulse width modulation by timer a1 by setting the pulse width modulation selection bit by timer a1 (bit 4) of the waveform output mode register to 1. the contents of the pulse output data register 0 can be reversed and output to pulse output ports rtp0 0 , rtp0 1 , rtp0 2 , and rtp0 3 by the polarity selection bit (bit 3) of the waveform output mode register. when the polarity selection bit is 0, the contents of the pulse output data register 0 is output unchangeably, and when 1, the contents of the pulse output data register 0 is reversed and output. when pulse width modulation is applied, likewise the polarity reverse to pulse width modulation can be selected by the polarity selection bit. fig. 4 waveform output mode register bit configuration fig. 5 timer a0, a2 mode register bit configuration in pulse output port mode fig. 6 pulse output data register bit configuration weveform output selection bit 0 0 : parallel port 0 1 : rtp1 selected 1 0 : rtp0 selected 1 1 : rtp1 and rtp0 selected pulse width modulation selection bit by timer a3 0 : not modulated 1 : modulated always ? 765432 0 1 weveform output mode register 62 16 address polarity selection bit 0 : positive polarity 1 : negative polarity pulse width modulation selection bit by timer a1 0 : not modulated 1 : modulated 0 always ?00?in pulse output port mode clock source selection bit 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 765432 0 1 timer a0 mode register 56 16 timer a2 mode register 58 16 address not used in pulse output port mode always ?0?in pulse output port mode 0 0 x 1 0 0 rtp0 0 output data 765432 0 1 address rtp0 1 output data rtp0 2 output data rtp0 3 output data pulse output data register 0 1d 16 rtp1 0 output data 765432 0 1 pulse output data register 1 1c 16 address rtp1 1 output data rtp1 2 output data rtp1 3 output data
9 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product fig. 7 example of waveforms in pulse output port mode output signal at each time when timer a2 becomes 0000 16 example of pulse output port (rtp1 0 ?rtp1 3 ) rtp1 3 (p5 7 ) rtp1 1 (p5 5 ) rtp1 0 (p5 4 ) rtp1 2 (p5 6 ) output signal at each time when timer a2 becomes 0000 16 example of pulse output port (rtp1 0 ?rtp1 3 ) when pulse width modulation is applied by timer a3. rtp1 3 (p5 7 ) rtp1 1 (p5 5 ) rtp1 0 (p5 4 ) rtp1 2 (p5 6 ) output signal at each time when timer a0 becomes 0000 16 example of pulse output port (rtp0 0 ?rtp0 3 ) when pulse width modulation is applied by timer a1 with polarity selection bit = ?? rtp0 3 (p5 3 ) rtp0 1 (p5 1 ) rtp0 0 (p5 0 ) rtp0 2 (p5 2 )
10 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product processor mode the bits 0 of processor mode register 0 as shown in figure 8 is used to select which mode of microprocessor mode, and evaluation chip mode. figure 9 shows functions of p0 0 /a 0 to p4 7 pins in each mode. the external memory area also changes when the mode changes. figure 10 shows the memory map for each mode. the accessing of the external memory is affected by the byte pin, the bit 2 (wait bit) of processor mode register 0, and bit 0 (wait selection bit) of processor mode register 1. ? byte pin when accessing the external memory, the level of the byte pin is used to determine whether to use the data bus as 8-bit width or 16- bit width. the data bus width is 8 bits when the level of the byte pin is h, and p2 0 /a 16 /d 0 to p2 7 /a 23 /d 7 pins become the data i/o pins. the data bus width is 16 bits when the level of the byte pin is l, and both p2 0 /a 16 /d 0 to p2 7 /a 23 /d 7 pins and p1 0 /a 8 /d 8 to p1 7 /a 15 / d 15 pins become the data i/o pins. when accessing the internal memory, the data bus width is always 16 bits regardless of the byte pin level. fig. 8 processor mode register bit configuration not used processor mode bit 0 : microprocessor mode 1 : evaluation chip mode wait bit 0 : wait 1 : no wait software reset bit reset occurs when this bit is set to 1 interrupt priority detection time selection bit 0 0 : internal clock 5 7 0 1 : internal clock 5 4 1 0 : internal clock 5 2 this bit must be 0 765432 0 1 0 processor mode register 0 address 5e 16 address 5f 16 processor mode register 1 wait selection bit 0 : wait 0 1 : wait 1 765432 0 1 1 this bit must be 1 (becomes 1 after reset release)
11 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product address a 0 -a 7 address data(odd) pm 1 pm 0 mode 1 0 1 1 microprocessor mode evaluation chip mode pin p0 0 /a 0 - p0 7 /a 7 p1 0 /a 8 /d 8 byte = l byte = h byte = l byte = h p0 0 /a 0 same as left a 8 to a 15 e e p0 7 /a 7 C p1 7 /a 15 /d 15 C p1 0 /a 8 /d 8 p1 7 /a 15 /d 15 C address a 8 -a 15 e p1 0 /a 8 /d 8 p1 7 /a 15 /d 15 C p2 0 /a 16 /d 0 p2 7 /a 23 /d 7 C address data(even) a 16 to a 23 e p2 0 /a 16 /d 0 p2 7 /a 23 /d 7 C address data(even, odd) a 16 to a 23 e p2 7 /a 23 /d 7 C p2 0 /a 16 /d 0 same as left p4 3 to p4 7 p4 2 / 1 , rdy, hold, address data(odd) a 8 to a 15 e p1 0 /a 8 /d 8 p1 7 /a 15 /d 15 C ports p4, p5 and their direction registers are treated as 16-bit wide bus. same as left address data(even, odd) a 16 to a 23 e p2 7 /a 23 /d 7 C p2 0 /a 16 /d 0 ports p4, p5 and their direction registers are treated as 16-bit wide bus. e p4 6 vpa dbc p4 7 p4 5 vda qcl p4 4 mx p4 3 p4 2 / 1 rdy hold hlda e p3 0 /r/w p3 1 /bhe e i/o port p4 3 p4 7 - p4 2 / 1 r/w bhe p3 2 /ale ale p3 3 /hlda hold hold rdy rdy p3 0 /r/ w , p3 1 / bhe , p3 2 /ale, p3 3 / hlda same as left (note) (note) fig. 9 relationship between pins p0 0 /a 0 to p4 7 and processor modes note. the signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the 1 output _ in the microprocessor mode. in the microprocessor mode, signal e can also be fixed to h when the internal memory area is accessed.
12 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product fig. 11 relationship between wait bit, wait selection bit, and access time ? wait bit as shown in figure 11, when the external memory area is accessed with the processor mode register 0 (address 5e 16 ) bit 2 (wait bit) cleared to 0, the access time can be extended compared with no wait (the wait bit is 1). the access time is extended in two ways and this is selected with bit 0 (wait selection bit) of processor mode register 1 (address 5f 16 ). when this bit is 1, the access time is 1.5 times compared to that for no wait. when this bit is 0, the access time is twice compared to that for no wait. at reset, the wait bit and the wait selection bit are 0. the accessing of internal memory area is performed in no wait mode regardless of the wait bit. the processor modes are described below. fig. 10 external memory area for each processor mode (1) microprocessor mode [10] microprocessor mode is entered by connecting the cnvss pin to vcc and starting from reset. __ signal e is output from pin e and is l during the data/instruction code read or data write term. when the internal memory area is read _ or written, e can be fixed to h by setting the signal output disable selection bit (bit 6 of oscillation circuit control register 0) to 1. p0 0 /a 0 to p0 7 /a 7 pins become address output pins. p1 0 /a 8 /d 8 to p1 7 /a 15 /d 15 pins have two functions depending on the level of the byte pin. when the byte pin level is l, p1 0 /a 8 /d 8 to p1 7 /a 15 /d 15 pins function _ as an address output pin while e is h and as an odd address data _ i/o pin while e is l. however, if an internal memory is read, external _ data is ignored while e is l. when the byte pin level is h, p1 0 /a 8 /d 8 to p1 7 /a 15 /d 15 pins function as an address output pin. when the byte pin level is l, p2 0 /a 16 /d 0 to p2 7 /a 23 /d 7 pins function _ as an address output pin while e is h and as an even address data _ i/o pin while e is l. however, if an internal memory is read, external _ data is ignored while e is l. _ r/ w is a read /write signal which indicates a read when it is h and a write when it is l. ___ bhe is a byte high enable signal which indicates that an odd address is accessed when it is l. therefore, two bytes at even and odd addresses are accessed ___ simultaneously if address a 0 is l and bhe is l. ale is an address latch enable signal used to latch the address signal from a multiplexed signal of address and data. the latch is transparent while ale is h to let the address signal pass through and held while ale is l. 80 16 80 16 87f 16 87f 16 sfr ram evaluation chip mode the shaded area is the external memory area. sfr 00 16 ffffff 16 ram microprocessor mode ffffff 16 2 16 a 16 c 16 wait bit 1 (no wait) internal clock ai/dj e ale ai/dj wait bit 0 (wait 1) e ale access time access time address data address data address data address data ai/dj wait bit 0 (wait 0) e ale access time address data address
13 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product ____ hlda is a hold acknowledge signal and is used to notify externally ____ when the microcomputer receives hold input and enters hold state. ____ hold is a hold request signal. it is an input signal used to put the ____ microcomputer in hold state. hold input is accepted when the internal clock falls from h level to l level while the bus is not used. p0 0 /a 0 to p0 7 /a 7 pins, p1 0 /a 8 /d 8 to p1 7 /a 15 /d 15 pins, p2 0 /a 16 /d 0 to _ ___ p2 7 /a 23 /d 7 pins, p3 0 /r/ w pin, and p3 1 / bhe pin are floating while the microcomputer stays in hold state. these pins are floating after one ____ cycle of the internal clock later than hlda signal changes to l level. at the removing of hold state, these ports are removed from ____ floating state after one cycle of internal clock later than hlda signal changes to h level. ___ rdy is a ready signal. if this signal goes l, the internal clock ___ stops at l. rdy is used when slow external memory is attached. p4 2 / 1 pin is an output pin for clock 1 . the 1 output is ___ independent of rdy and does not stop even when internal clock ___ stops because of l input to the rdy pin. as shown in table 2, 1 output can also be stopped with the signal output disable selection bit 1. in this case, write 1 to the port p4 2 direction register. (2) evaluation chip mode [11] evaluation chip mode is entered by applying voltage twice the v cc voltage to the cnv ss pin. this mode is normally used for evaluation tools. _ _ ___ ____ the functions of e , p0 0 /a 0 to p0 7 /a 7 pins, r/ w , bhe , ale, and hlda are the same as those in microprocessor mode. p1 0 /a 8 /d 8 to p1 7 /a 15 /d 15 pins function as address output pins while __ e is h and as data i/o pin of odd addresses while e is l regardless of the byte pin level. however, if an internal memory is read, external _ data is ignored while e is l. p2 0 /a 16 /d 0 to p2 7 /a 23 /d 7 pins function _ as address output pins while e is h and as data i/o pin of even _ addresses while e is l when the byte pin level is l. however, if _ an internal memory is read, external data is ignored while e is l. when the byte pin level is h or 2?v cc , port p2 functions as an _ address output pin while e is h and as data i/o pin of even and odd _ addresses while e is l. however, if an internal memory is read, _ external data is ignored while e is l. port p4 and its data direction which are located at address 0a 16 and 0c 16 are treated differently in evaluation chip mode. when these addresses are accessed, the data bus width is treated as 16 bits regardless of the byte pin level, and the access cycle is treated as internal memory regardless of the wait bit. ____ ___ the functions of hold and rdy are the same as those in microprocessor mode. clock 1 from p4 2 / 1 pin is always output regardless of signal output disable selection bit. ports p4 3 to p4 6 become mx, qcl, vda, and vpa output pins ___ respectively. port p4 7 becomes the dbc input pin. the mx signal normally contents of flag m, but the contents of flag x is output if the cpu is using flag x. qcl is the queue buffer clear signal. it becomes h when the instruction queue buffer is cleared, for example, when a jump instruction is executed. vda is the valid data address signal. it becomes h while the cpu is reading data from data buffer or writing data to data buffer. it also becomes h when the first byte of the instruction (operation code) is read from the instruction queue buffer. vpa is the valid program address signal. it becomes h while the cpu is reading an instruction code from the instruction queue buffer. ___ dbc is the debug control signal and is used for debugging. table 1 shows the relationship between the cnv ss pin input levels and processor modes. table 1. relationship between cnvss pin input levels and processor modes cnvss mode description ? microprocessor (? evaluation chip) vss microprocessor mode upon starting after reset. 2 ? vcc ? evaluation chip evaluation chip mode only. _ e _ e is output when the internal/external memory _ e is output only when the external memory area is accessed. area is accessed. after wit/stp instruction is executed, l is output after wit/stp instruction is h is output. executed. microprocessor mode * standby state selection bit (bit 0 of port function control register) must be set to 1. 1 clock 1 is output. hor l is output. (output the content of p4 2 latch.) * port p4 2 direction register must be set to 1. table 2. function of signal output disable selection bit cm 6 (bit 6 of oscillation circuit control register 0) function cm 6 = 0 cm 6 = 1 processor mode pin note. functions shown in table 2 cannot be emulated in a debugger.
14 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product reset circuit _____ the microcomputer is released from the reset state when the reset pin is returned to h level after holding it at l level with the power source voltage at 5 v 10 %. program execution starts at the address formed by setting address a 23 C a 16 to 00 16 , a 15 C a 8 to the contents of address ffff 16 , and a 7 C a 0 to the contents of address fffe 16 . figure 12 shows the status of the internal registers during reset. figure 13 shows an example of a reset circuit. if the stabilized clock is input from the external to the main-clock oscillation circuit, the reset input voltage must be 0.9 v or less when the power source voltage reaches 4.5 v. if a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from l to h after the main-clock oscillation is fully stabilized. fig. 12 microcomputer internal status during reset address 00 16 00 00 00 16 00 16 00 16 00 16 00 16 00 16 0 11 00 00 0 0 ??? 00 16 00 16 0 00 00 00 00 00 00 00 00 10 00 00 10 00 00 10 10 00 16 000 0 0 00 16 00 16 00 16 00 16 00 16 00 16 0 001 00 0 0 001 001 00 0 0 00 0 0 0 00 16 (04 16 ) (05 16 ) (08 16 ) (09 16 ) (0c 16 ) (0d 16 ) (10 16 ) (11 16 ) (14 16 ) (1e 16 ) (1f 16 ) (30 16 ) (38 16 ) (34 16 ) (3c 16 ) (35 16 ) (3d 16 ) (40 16 ) (42 16 ) (44 16 ) (56 16 ) (57 16 ) (58 16 ) (59 16 ) (5a 16 ) (5b 16 ) (5c 16 ) (5d 16 ) (5e 16 ) (5f 16 ) port p0 direction register port p1 direction register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register a-d control register 0 a-d control register 1 uart 0 transmit/receive mode register uart 1 transmit/receive control register 1 uart 1 transmit/receive mode register uart 0 transmit/receive control register 0 uart 1 transmit/receive control register 0 uart 0 transmit/receive control register 1 count start flag one- shot start flag up-down flag timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 processor mode register 1 address (7f 16 ) (61 16 ) (6c 16 ) (6d 16 ) (6e 16 ) (6f 16 ) (70 16 ) (71 16 ) (72 16 ) (73 16 ) (74 16 ) (75 16 ) (76 16 ) (77 16 ) (78 16 ) (79 16 ) (7a 16 ) (7b 16 ) (7c 16 ) (7d 16 ) (7e 16 ) watchdog timer frequency selection flag oscillation circuit control register 0 port function control register serial transmit control register oscillation circuit control register 1 a-d/uart2 trans./rece. interrupt control register uart 0 transmission interrupt control register uart 0 receive interrupt control register uart 1 transmission interrupt control register uart 1 receive interrupt control register timer a0 interrupt control register timer b2 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register processor status register (ps) program bank register (pg) program counter (pc h ) program counter (pc l ) direct page register (dpr) data bank register (dt) int 0 interrupt control register int 1 interrupt control register int 2 /key input interrupt control register 0 contents of other registers and ram are undefined during reset. initialize them by software. ? 0 0 0 00 00 0 ? 0 01 000 000 000 000 1?? 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 0 0 00 00 0 0 0 00 16 00 16 content of ffff 16 content of fffe 16 0000 16 0 0 0 0 0 0 00 16 (60 16 ) watchdog timer register fff 16 waveform output mode register uart2 transmit/receive mode register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 (62 16 ) 0 (64 16 ) 0 (68 16 ) 0 (69 16 ) 0 0 0 0 00 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 00 16
15 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product fig. 13 example of a reset circuit v cc reset reset v cc 0v 0v 4.5v 0.9v power on note. in this case, stabilized clock is input from the external to the main-clock oscillation circuit. perform careful evalvation at the system design level before using. addressing modes the M37733S4BFP has 28 powerful addressing modes. refer to the mitsubishi semiconductors data book single - chip 16-bit microcomputers for the details of each addressing mode. machine instruction list the M37733S4BFP has 103 machine instructions. refer to the mitsubishi semiconductors data book single - chip 16-bit microcomputers for details.
16 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product limits min. typ. max. f(x in ) : operating 4.5 5.0 5.5 f(x in ) : stopped, f(x cin ) = 32.768 khz 2.7 5.5 avcc analog power source voltage vcc v vss power source voltage 0v avss analog power source voltage 0 v high-level input voltage ___ ___ hold , rdy , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , ____ p8 0 C p8 7 , x in , reset , cnvss, byte, x cin (note 3) high-level input voltage p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 ___ ___ low-level input voltage hold , rdy , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , ____ p8 0 C p8 7 , x in , reset , cnvss, byte, x cin (note 3) low-level input voltage p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 high-level peak output current p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , _ ___ p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p3 0 /r/ w , p3 1 / bhe , ___ p3 2 /ale, p3 3 / hlda , p4 2 / 1 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 5 , p8 0 C p8 7 high-level average output current p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , _ ___ p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p3 0 /r/ w , p3 1 / bhe , ____ p3 2 /ale, p3 3 / hlda , p4 2 / 1 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 5 , p8 0 C p8 7 low-level peak output current p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , _ ___ p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p3 0 /r/ w , p3 1 / bhe , ____ p3 2 /ale, p3 3 / hlda , p4 2 / 1 , p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 5 , p8 0 C p8 7 low-level peak output current p4 4 C p4 7 , p5 0 C p5 3 low-level average output current p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , _ ___ p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p3 0 /r/ w , p3 1 / bhe , ____ p3 2 /ale, p3 3 / hlda , p4 2 / 1 , p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 5 , p8 0 C p8 7 i ol(avg) low-level average output current p4 4 C p4 7 , p5 0 C p5 3 15 ma f(x in ) main-clock oscillation frequency (note 4) 25 mhz f(x cin) sub-clock oscillation frequency 32.768 50 khz symbol parameter conditions ratings unit vcc power source voltage C0.3 to +7 v avcc analog power source voltage C0.3 to +7 v v i ____ input voltage reset , cnvss, byte C0.3 to +12 v input voltage p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , ___ ___ p8 0 C p8 7 , v ref , x in , hold , rdy output voltage p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , _ p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p3 0 /r/ w , __ ___ p3 1 / bhe , p3 2 /ale, p3 3 / hlda , p4 2 / 1 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , _ p7 0 C p7 7 , p8 0 C p8 7 , x out , e p d power dissipation ta = 25 c 300 mw t opr operating temperature C20 to +85 c t stg storage temperature C40 to +150 c unit recommended operating conditions (vcc = 5 v 10 %, ta = C20 to +85 c, unless otherwise noted) v notes 1. average output current is the average value of a 100 ms interval. _ ___ 2. the sum of i ol(peak) for ports p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p3 0 /r/ w , p3 1 / bhe , p3 2 /ale, p3 3 / ____ hlda and p8 must be 80 ma or less, the sum of i oh(peak) for ports p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 16 /d 0 C p2 7 /a 23 / _ ___ ____ d 7 , p3 0 /r/ w , p3 1 / bhe , p3 2 /ale, p3 3 / hlda and p8 must be 80 ma or less, the sum of i ol(peak) for ports p4, p5, p6, and p7 must be 100 ma or less, and the sum of i oh(peak) for ports p4, p5, p6, and p7 must be 80 ma or less. 3. limits v ih and v il for x cin are applied when the sub clock external input selection bit = 1. 4. the maximum value of f(x in ) = 12.5 mhz when the main clock division selection bit = 1. 0.8 vcc 0.5 vcc 0 0 v v v v ma ma ma ma ma absolute maximum ratings v i v o C0.3 to vcc + 0.3 v C0.3 to vcc + 0.3 v parameter symbol vcc power source voltage vcc vcc 0.2vcc 0.16vcc v ih v ih v il v il i oh(peak) i oh(avg) i ol(peak) i ol(peak) i ol(avg) C10 C5 10 20 5
17 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product unit electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to +85 c, f(x in ) = 25 mhz, unless otherwise noted) symbol parameter test conditions 3 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 0.1 C0.25 2 2 2 0.45 1.9 0.43 1.6 0.4 1 0.5 0.4 0.4 5 C5 C5 C1.0 i oh = C10 ma i oh = C400 a i oh = C10 ma i oh = C400 a i oh = C10 ma i oh = C400 a i ol = 10 ma i ol = 20 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v cc = 5 v v i = 5 v v i = 0 v v i = 0 v, without a pull-up transistor v i = 0 v, with a pull-up transistor when clock is stopped high-level output voltage p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , ___ p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p3 3 / hlda , p4 2 / 1 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 high-level output voltage p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , ___ p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p3 3 / hlda , p4 2 / 1 _ ___ high-level output voltage p3 0 /r/ w , p3 1 / bhe , p3 2 /ale _ high-level output voltage e low-level output voltage p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , ___ p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p3 3 / hlda , p4 2 / 1 , p4 3 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 low-level output voltage p4 4 C p4 7 , p5 0 C p5 3 low-level output voltage p0 0 /a 0 C p0 7 /a 7 , p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , ___ p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p3 3 / hlda , p4 2 / 1 _ ___ low-level output voltage p3 0 /r/ w , p3 1 / bhe , p3 2 /ale _ low-level output voltage e hysteresis ____ ___ hold , rdy , ta0 in C ta4 in , tb0 in C tb2 in , ___ ___ ____ ____ ____ ____ int 0 C int 2 , ad trg , cts 0 , cts 1 , cts 2 , clk 0 , __ __ clk 1 , clk 2 , ki 0 C ki 3 _____ hysteresis reset hysteresis x in hysteresis x cin (when external clock is input) high-level input current p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p4 3 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 , ____ x in , reset , cnvss, byte low-level input current p1 0 /a 8 /d 8 C p1 7 /a 15 /d 15 , p2 0 /a 16 /d 0 C p2 7 /a 23 /d 7 , p4 3 C p4 7 , p5 0 C p5 3 , p6 0 , p6 1 , p6 5 C p6 7 , p7 0 C p7 7 , ____ p8 0 C p8 7 , x in , reset , cnvss, byte low-level input current p5 4 C p5 7 , p6 2 C p6 4 ram hold voltage v oh v oh v oh v oh v ol v ol v ol v ol v ol v t+ C v tC v t+ C v tC v t+ C v tC v t+ C v tC i ih i il i il v ram C0.5 v v v v v v v v v v v v v v v a a a ma v limits typ. max. min.
18 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product v cc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 12.5 mhz), f(x cin ) = 32.768 khz, in operating (note 1) v cc = 5 v, f(x in ) = 25 mhz (square waveform), (f(f 2 ) = 1.5625 mhz), f(x cin ) = stopped, in operating (note 1) v cc = 5 v, f(x in ) = 25 mhz (square waveform), f(x cin ) = 32.768 khz, when a wit instruction is executed (note 2) v cc = 5 v, f(x in ) = stopped, f(x cin ) = 32.768 khz, in operating (note 3) v cc = 5 v, f(x in ) = stopped, f(x cin ) = 32.768 khz, when a wit instruction is executed (note 4) ta = 25 c, when clock is stopped ta = 85 c, when clock is stopped ma ma a a a a a max. 22.8 3.2 20 120 10 1 20 limits typ. 11.4 1.6 10 60 5 unit min. test conditions symbol parameter electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to +85 c, unless otherwise noted) when external bus is in use, output pins are open, and other pins are v ss . power source current i cc limits min. typ. max. resolution v ref = v cc 10 bits absolute accuracy v ref = v cc 3 lsb r ladder ladder resistance v ref = v cc 10 25 k w t conv conversion time 9.44 s v ref reference voltage 2 v cc v v ia analog input voltage 0 v ref v symbol parameter test conditions unit aCd converter characteristics (v cc = av cc = 5 v, v ss = av ss = 0 v, ta = C20 to +85 c, f(x in ) = 25 mhz, unless otherwise noted (note)) note. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. notes 1. this applies when the main clock external input selection bit = 1, the main clock division selection bit = 0, and the signal output stop bit = 1. 2. this applies when the main clock external input selection bit = 1 and the system clock stop bit at wait state = 1. 3. this applies when cpu and the clock timer are operating with the sub clock (32.768 khz) selected as the system clock. 4. this applies when the x cout drivability selection bit = 0 and the system clock stop bit at wait state = 1.
19 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product limits min. max. t c external clock input cycle time (note 1) 40 ns t w(h) external clock input high-level pulse width (note 2) 15 ns t w(l) external clock input low-level pulse width (note 2) 15 ns t r external clock rise time 8ns t f external clock fall time 8ns timing requirements (v cc = 5 v 10 %, v ss = 0 v, ta = C20 to +85 c, f(x in ) = 25 mhz, unless otherwise noted (note 1)) notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mh z . 2. input signals rise/fall time must be 100 ns or less, unless otherwise noted. external clock input unit symbol parameter notes 1. when the main clock division selection bit = 1, the minimum value of tc = 80 ns. 2. when the main clock division selection bit = 1, values of tw (h) / tc and tw (l) / tc must be set to values from 0.45 through 0.55. microprocessor mode unit symbol parameter limits min. max. t su(p4dCe) port p4 input setup time 60 ns t su(p5dCe) port p5 input setup time 60 ns t su(p6dCe) port p6 input setup time 60 ns t su(p7dCe) port p7 input setup time 60 ns t su(p8dCe) port p8 input setup time 60 ns t h(eCp4d) port p4 input hold time 0ns t h(eCp5d) port p5 input hold time 0ns t h(eCp6d) port p6 input hold time 0ns t h(eCp7d) port p7 input hold time 0ns t h(eCp8d) port p8 input hold time 0ns t su(dCe) data input setup time 32 ns t su(rdyC 1) ___ rdy input setup time 55 ns t su(holdC 1) ____ hold input setup time 55 ns t h(eCd) data input hold time 0ns t h( 1Crdy) ___ rdy input hold time 0ns t h( 1Chold) ____ hold input hold time 0ns
20 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product limits min. max. t c(ta) tai in input cycle time 80 ns t w(tah) tai in input high-level pulse width 40 ns t w(tal) tai in input low-level pulse width 40 ns unit symbol parameter timer a input (count input in event counter mode) limits min. max. t c(ta) tai in input cycle time (note) 320 ns t w(tah) tai in input high-level pulse width (note) 160 ns t w(tal) tai in input low-level pulse width (note) 160 ns unit symbol parameter timer a input (gating input in timer mode) note. limits change depending on f(x in ). refer to data formulas. limits min. max. t c(ta) tai in input cycle time (note) 320 ns t w(tah) tai in input high-level pulse width 80 ns t w(tal) tai in input low-level pulse width 80 ns unit symbol parameter timer a input (external trigger input in one-shot pulse mode) note. limits change depending on f(x in ). refer to data formulas. limits min. max. t w(tah) tai in input high-level pulse width 80 ns t w(tal) tai in input low-level pulse width 80 ns unit symbol parameter timer a input (external trigger input in pulse width modulation mode) limits min. max. t c(up) tai out input cycle time 2000 ns t w(uph) tai out input high-level pulse width 1000 ns t w(upl) tai out input low-level pulse width 1000 ns t su(upCt in ) tai out input setup time 400 ns t h(t in Cup) tai out input hold time 400 ns unit symbol parameter timer a input (up-down input in event counter mode) limits min. max. t c(ta) taj in input cycle time 800 ns t su(taj in Ctaj out ) taj in input setup time 200 ns t su(taj out Ctaj in ) taj out input setup time 200 ns unit symbol parameter timer a input (two-phase pulse input in event counter mode)
21 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product limits min. max. t c(tb) tbi in input cycle time (one edge count) 80 ns t w(tbh) tbi in input high-level pulse width (one edge count) 40 ns t w(tbl) tbi in input low-level pulse width (one edge count) 40 ns t c(tb) tbi in input cycle time (both edges count) 160 ns t w(tbh) tbi in input high-level pulse width (both edges count) 80 ns t w(tbl) tbi in input low-level pulse width (both edges count) 80 ns unit symbol parameter timer b input (count input in event counter mode) limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse period measurement mode) limits min. max. t c(tb) tbi in input cycle time (note) 320 ns t w(tbh) tbi in input high-level pulse width (note) 160 ns t w(tbl) tbi in input low-level pulse width (note) 160 ns unit symbol parameter timer b input (pulse width measurement mode) note. limits change depending on f(x in ). refer to data formulas. limits min. max. t c(ck) clk i input cycle time 200 ns t w(ckh) clk i input high-level pulse width 100 ns t w(ckl) clk i input low-level pulse width 100 ns t d(cCq) t x d i output delay time 80 ns t h(cCq) t x d i hold time 0ns t su(dCc) r x d i input setup time 30 ns t h(cCd) r x d i input hold time 90 ns unit symbol parameter a-d trigger input unit symbol parameter serial i/o unit symbol parameter ____ ___ external interrupt int i input, key input interrupt ki i input limits min. max. t w(inh) ___ int i input high-level pulse width 250 ns t w(inl) ___ int i input low-level pulse width 250 ns t w(kil) __ ki i input low-level pulse width 250 ns limits min. max. t c(ad) ____ ad trg input cycle time (minimum allowable trigger) 1000 ns t w(adl) ____ ad trg input low-level pulse width 125 ns note. limits change depending on f(x in ). refer to data formulas.
22 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product data formulas timer a input (gating input in timer mode) 8 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) limits min. max. symbol parameter unit t c(ta) tai in input cycle time t w(tah) tai in input high-level pulse width t w ( tal ) tai in input low-level pulse width ns ns ns 8 5 10 9 2 ? f(f 2 ) timer a input (external trigger input in one-shot pulse mode) limits min. max. symbol parameter unit t c(ta) tai in input cycle time ns timer b input (in pulse period measurement mode or pulse width measurement mode) limits min. max. symbol parameter unit ns ns ns t c(tb) tbi in input cycle time t w(tbh) tbi in input high-level pulse width t w(tbl) tbi in input low-level pulse width 8 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) note. f(f 2 ) expresses the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 9 in data sheet m37733mhbxxxfp.
23 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product switching characteristics (v cc = 5 v 10 %, v ss = 0 v, ta = C20 to +85c, f(x in ) = 25 mhz, unless otherwise noted (note)) unit symbol parameter test conditions note. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. limits min. max. t d(eCp4q) port p4 data output delay time 80 ns t d(eCp5q) port p5 data output delay time 80 ns t d(eCp6q) port p6 data output delay time 80 ns t d(eCp7q) port p7 data output delay time 80 ns t d(eCp8q) port p8 data output delay time 80 ns microprocessor mode fig. 14 measuring circuit for each pin 50 pf a 0 C a 7 a 8 /d 8 C a 23 /d 7 r/ w bhe ale hlda p 4 p 5 p 6 p 7 p 8 1 e fig. 14
24 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold time _ e pulse width floating start delay time floating release delay time ___ bhe output delay time _ r/ w output delay time ___ bhe hold time _ r/ w hold time 1 output delay time ____ hlda output delay time no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC 1 ) t d( 1 Chlda) limits wait mode min. max. microprocessor mode (v cc = 5 v 10 %, v ss = 0 v, ta = 25 c, f(x in ) = 25 mhz, unless otherwise noted (note 1)) symbol parameter test conditions unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45 5 18 50 fig. 14 12 87 12 75 18 22 57 5 45 9 15 4 10 18 50 130 20 12 87 12 87 18 18 0 notes 1. this applies when the main clock division selection bit = 0 and f(f 2 ) = 12.5 mhz. 2. no wait : wait bit = 1. wait 1 : the external memory area is accessed with wait bit = 0 and wait selection bit = 1. wait 0 : the external memory area is accessed with wait bit = 0 and wait selection bit = 0. (note2)
25 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product 0 1 5 10 9 2 ? f(f 2 ) t d(anCe) t d(aCe) t h(eCan) t w(ale) t su(aCale) t h(aleCa) t d(aleCe) t d(eCdq) t h(eCdq) t w(el) t pxz(eCdz) t pzx(eCdz) t d(bheCe) t d(r/wCe) t h(eCbhe) t h(eCr/w) t d(eC 1 ) address output delay time address output delay time address hold time ale pulse width address output setup time address hold time ale output delay time data output delay time data hold time _ e pulse width floating start delay time floating release delay time ___ bhe output delay time _ r/ w output delay time ___ bhe hold time _ r/ w hold time 1 output delay time ns ns ns ns ns ns ns ns 45 5 18 bus timing data formulas (v cc = 5 v 10 %, v ss = 0 v, ta = C20 to +85 c, f(x in ) = 25 mhz (max.), unless otherwise noted (note 1)) limits wait mode min. max. symbol parameter unit 1 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) ns ns ns ns ns ns ns ns ns ns 1 5 10 9 2 ? f(f 2 ) ns ns ns ns ns ns 9 4 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 2 5 10 9 2 ? f(f 2 ) 4 5 10 9 2 ? f(f 2 ) ns ns C 28 C 33 C 28 C 45 C 22 C 18 C 23 C 35 C 35 C 25 C 30 C 22 C 30 C 30 C 22 C 28 C 33 C 28 C 33 C 22 C 22 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 no wait wait 1 wait 0 notes 1. this applies when the main-clock division selection bit = 0. 2. f(f 2 ) expresses the clock f 2 frequency. for the relation to the main clock and sub clock, refer to table 9 in data sheet m37733mhbxxxfp. 1 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 ) 3 5 10 9 2 ? f(f 2 ) 1 5 10 9 2 ? f(f 2 )
26 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product t w(h) t d(eCp4q) t d(eCp5q) t d(eCp6q) t d(eCp7q) t d(eCp8q) e x in port p4 output port p4 input port p5 output port p5 input port p6 output port p6 input port p7 output port p7 input port p8 output port p8 input t su(p4dCe) t su(p5dCe) t su(p6dCe) t su(p7dCe) t su(p8dCe) t r t f t w(l) t c t h(eCp4d) t h(eCp5d) t h(eCp6d) t h(eCp7d) t h(eCp8d) timing diagram
27 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product tai in input tai out input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in ?p) t su(up? in ) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) in event count mode t c(tb) t w(tbh) t w(tbl) tbi in input t su(taj in ?aj out ) t su(taj in ?aj out ) t su(taj out ?aj in ) t su(taj out ?aj in ) taj in input taj out input in event counter mode (when two-phase pulse input is selected) t c(ta)
28 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(knl) t d(c?) t su(d?) t h(c?) t w(inh) ad trg input clk i txd i rxd i inti input kli input t h(c?)
29 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product microprocessor mode (when wait bit = 1) (when wait bit = 0) (when wait bit = 1 or 0 in common) test conditions ? v cc = 5 v 10 % ? input timing voltage : v il = 1.0 v, v ih = 4.0 v ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v 1 rdy input 1 e rdy input 1 hold input hlda output t su(rdyC 1 ) t h( 1 Crdy) t su(rdyC 1 ) t h( 1 Crdy) t su(holdC 1 ) t d( 1 Chlda) t h( 1 Chold) t d( 1 Chlda) e
30 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product t h(eCdq) t w(l) t w(h) t f t r t c microprocessor mode (no wait : when wait bit = 1) x in 1 an ale am/dm t w(ale) t d(aleCe) t su(aCale) t h(aleCa) t d(aCe) t pxz(eCdz) t pzx(eCdz) address data address address t h(eCan) t d(eCdq) dm in test conditions ? vcc = 5 v 10 % ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v t su(dCe) t h(eCd) data address t d(anCe) address address t d(eC 1 ) t d(eC 1 ) t d(bheCe) t h(eCbhe) t d(r/wCe) t h(eCr/w) e t w(el) bhe r/ w
31 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product t w(ale) t d(anCe) t c am/dm address t w(l) t w(h) t f t r microprocessor mode (wait 1 : the external memory area is accessed when wait bit = 0 and wait selection bit = 1.) x in 1 address address an ale dm in r/ w t d(eC 1 ) t d(aleCe) t su(aCale) t h(aleCa) t d(aCe) t d(eCdq) t pxz(eCdz) t pzx(eCdz) t h(eCd) t su(dCe) t d(r / wCe) t h(eCr/w) test conditions ? vcc = 5 v 10 % ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v data address data t d(eC 1 ) t h(e-an) t w(el) e bhe t d(bheCe) t h(eCbhe) address t h(eCdq) address
32 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product t h(aleCa) t d(aleCe) t d(eCdq) t w(l) t w(h) t f t c t r microprocessor mode (wait 0 : the external memory area is accessed when wait bit = 0 and wait selection bit = 0.) x in 1 address address address address data e an ale am/dm dm in bhe t d(anCe) t w(ale) t h(eCan) t su(aCale) t h(eCdq) t d(aCe) t pxz(eCdz) t pzx(eCdz) t h(eCd) t su(dCe) t d(bheCe) t h(eCbhe) address data address test conditions ? vcc = 5 v 10 % ? output timing voltage : v ol = 0.8 v, v oh = 2.0 v ? data input dm in : v il = 0.8 v, v ih = 2.5 v t d(eC 1 ) t d(eC 1 ) t w(el) t d(r/wCe) t h(eCr/w) r/ w
33 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product package outline
34 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product memo
35 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product memo
36 mitsubishi microcomputers M37733S4BFP 16-bit cmos microcomputer new product ? 1996 mitsubishi electric corp. h-lf432-a ki-9607 printed in japan (rod) new publication, effective jul. 1996. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

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